Tools and other resources

This post contains links for opensource projects, tools that might be interesting for functional verification, digital design modeling, etc.

resource	links	comments
Wavedrom	wavedrom editor	web-service allows to draw pretty waveforms right from browser, simple&elegant
kactus ip-xact	kactus at sourceforge	Qt-editor for ip-xact creation and MCAPI(?). The app is eye pleasing, but still lacks some features like creation memorymaps and register editing. Regretfully, guys use Qt>4.7 which may be a showstopper for enterprise solutions (scores,hundreds of working PC) where RHEL 4,5,6 are dominating OS. As of CentOS 6 yum repos contain only Qt 4.6.
sveditor	sveditor at sourceforge	eclipse plugin for systemverilog, more info about installing can be found at this blog

Books & Articles

this article will be updated on&off

General Programming

• Code Complete by Steve McConnell
• Design Patterns: Elements of Reusable Object-Oriented Software by Erich Gamma, Richard Helm, Ralph Johnson and John Vlissides (GOF)

C/C++ Programming

• Thinking in C++: Introduction to Standard C++ by Bruce Eckel (available for free download)

Python Programming

• Dive into Python by Mark Pilgrim (available for free download)

SystemVerilog & Verification

• SYSTEMVERILOG FOR VERIFICATION A Guide to Learning the Testbench Language Features by Chris Spear. The book is an excellent introduction into SV language features for verification: multithreading support, coverage & randomization features are explained with rich examples and detailed comments.
• AVM Cookbook by Mark Glasser, Adam Rose, Tom Fitzpatrick, Dave Rich, Harry Foster. Advanced Verification Methodology (AVM) is predecessor for OVM (which is in turn 'father' of UVM). AVM was developed by Mentor. Actually I wasn't able to find the book from Mentor site, probably a direct e-mail request should do the trick. The book was available for free download, a registration was required though. I truely recommend the book for beginners. It has many conceptual features for verification explained (OOP, TLM,monitors, TLM->RTL refinement, randomization). To compare, UVM cookbook doesn't explain TLM at all, it shows off examples HOW to use TLM classes, but not WHY they should be used (as of uvm1.1 uvm cookbook looks like a bunch of notes piled by different people). UPDATE: as this post points avm cookbook probably can be downloaded here after registration.

SystemVerilog & RTL Design

• SystemVerilog For Design Second Edition A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland.

Blogs I follow

• Coolverification
• verilab